Keying signal generator with false output immunity

ABSTRACT

A circuit for generating a composite keying signal comprises a gate pulse generating circuit and a voltage translating network in a television receiver also including keyed video signal processing circuits. The composite keying signal comprises a first pulse developed by the translating network during horizontal blanking intervals of the video signal, and a second pulse developed by the gate circuit during a portion of the horizontal blanking intervals and superimposed on the first pulse. An output of the gate circuit is clamped during picture intervals to a fixed voltage via a low impedance clamping path that exhibits current conduction capability greater than the output current conduction capability of the gate pulse generating circuit. The clamping action prevents improper keying of the keyed circuits in response to false keying signals such as may be generated in response to spurious signals occurring during picture intervals of the television signal.

This invention concerns a circuit arrangement for developing a keyingsignal such as a composite signal from which multiple keying signals canbe derived, for use in a television receiver including keyed circuits.In particular, the invention concerns an improvement of such a circuitas disclosed in a copending U.S. patent application Ser. No. 113,371 ofR. L. Shanley, II, et al. entitled "Controlled Output Composite KeyingSignal Generator For A Television Receiver," and now U.S. Pat. No.4,263,610, wherein the circuit output is controllably suppressed duringpicture intervals of the video signal to inhibit false output keyingsignals such as may occur during the picture intervals.

In a color television receiver for processing a composite colortelevision signal including luminance, chrominance and synchronizingsignal components, there is a need for signal processing functions thatrequire keying or synchronization with respect to the compositetelevision signal. In pertinent part, these functions include keying toseparate the burst and chrominance information components of thecomposite signal, keying a blanking level clamp during image blankingintervals to establish a black reference level for a displayed picture,and keying during horizontal and vertical retrace blanking intervals toinhibit image display during these intervals.

When keyed luminance or chrominance signal processing circuits of thereceiver are contained within an integrated circuit in whole or insignificant part, it is desirable to provide a single, composite keyingsignal from which signals for performing the described keying functionscan be derived. A single, composite keying signal of this type isdesirable since only a single external keying signal input terminal ofthe integrated circuit is then required. Also, an integrated circuitincorporating a composite keying signal generator requires only oneoutput terminal for providing the composite keying signal.

Such a composite keying signal is known, and if often referred to as a"sandcastle" signal because of its configuration. The sandcastle keyingsignal typically comprises a first pulse component of a given width, anda second pulse component of lesser width superimposed on the first pulsecomponent. The first and second pulse components exhibit givenamplitudes and timing in accordance with the keying and synchronizingrequirements of signal processing circuits within the receiver.

In accordance with the principles of the present invention, it is hereinrecognized as being desirable to prevent improper keying of the keyedreceiver circuits in response to a keying signal of the type describedabove. Such improper keying can occur if the keying signal generator iscaused to produce an output keying signal during picture intervals ofthe video signal. This may occur, for example, in response to spurioussignals such as noise and other effects occurring during the pictureinterval.

Keying apparatus according to the present invention is included in atelevision receiver for processing a composite television signalcontaining image information occurring during periodic image intervals,and horizontal synchronizing information occurring during periodichorizontal image blanking intervals. The receiver includes a network forproviding a horizontal reference pulse representative of the horizontalsynchronizing information, a source of horizontal timing signals withimage and blanking components and subject to synchronization by thehorizontal synchronizing information, and keyed signal processingcircuits.

The keying apparatus generates keying signals during the horizontalblanking intervals, and includes a keyed circuit and a control circuit.The keyed circuit is coupled to the network which provides thehorizontal reference pulse and is subject to switching between first andsecond switching states for generating the keying signals. The keyedcircuit includes an output circuit coupled to a circuit point, andexhibits the second switching state during the appearance of eachreference pulse. Keying signals developed by the keyed circuit arecoupled from the circuit point to the keyed signal processing circuits.The control circuit is coupled to the circuit point and responds to thehorizontal timing signals for inhibiting false keying signal outputsfrom the keyed circuit during the image intervals. The control circuitexhibits nonconductive and conductive states during the blanking andimage intervals, respectively. The current conduction capability of thecontrol circuit during image intervals substantially equals or exceedsthe current conduction capability of the output circuit of the keyedcircuit.

In accordance with a feature of the invention, the control circuitexhibits a lower impedance during the image intervals than the impedancepresented by the output circuit when the keyed circuit exhibits thesecond switching state.

In accordance with another feature of the invention, the control circuitcomprises a clamping network coupled between the circuit point and apoint of reference potential. The keyed circuit and the clamping networkare arranged so that currents conducted by the output circuit of thekeyed circuit in response to false keying signals, when present duringimage intervals, are poled so as to reinforce clamping currentsconducted by the clamping network during image intervals.

In the drawing:

FIG. 1 shows a block diagram of a system including a color televisionreceiver comprising apparatus according to the present invention; and

FIG. 2 illustrates a circuit diagram of a keying signal generatoraccording to the invention.

In FIG. 1, a source of composite color television signals 10, (e.g.,including RF and IF amplifier and video detector stages of a colortelevision receiver) supplies signals to a luminance-chrominance signalseparator 12. Separator 12 (e.g., a comb filter) separates the luminanceand chrominance components of the composite television signal, andsupplies these separated components to respective input terminals 1 and2 of a luminance and chrominance signal processing network 11.

The separated luminance component is processed by a luminance signalprocessing unit 14 in a luminance channel of the receiver, includingsignal amplification and peaking stages for example. The separatedchrominance component is supplied to a keyed chrominance-burst separator15, which provides separated burst information (B) and chrominancepicture interval information (C). Signal separation 15 can be of thetype described in U.S. Pat. No. 4,038,681 of L. A. Harwood. Theseparated signals are then supplied to a chrominance signal processingunit 18 for developing r-y, g-y and b-y color difference signals asknown. The color difference signals from unit 18 are combined with anamplified luminance output signal (Y) from unit 14 in a signal matrix20, for developing output r, b and g color image signals.

The luminance channel also includes a blanking level clamp comprising akeyed comparator 30 which is keyed during the burst interval of eachvideo signal horizontal blanking interval. When keyed, comparator 30samples and compares a brightness reference voltage V_(REF) with theD.C. level of the signal then appearing at the b (blue) signal output ofmatrix 20. An output signal from comparator 30 is supplied to a controlinput of luminance processor 14, for establishing the blanking level ofthe luminance signal (and thereby picture brightness) at a correct levelin accordance with the level of voltage V_(REF). The arrangement ofcomparator 30 with luminance processor 14 and matrix 20 is described indetail in U.S. Pat. No. 4,197,557 of A. V. Tuma, et al.

The r, g, b color signals from matrix 20 are separately coupled viaplural output networks included in an output unit 22, to outputterminals 3, 4 and 5 of network 11. The color signals are amplifiedindividually by amplifiers within a kinescope driver stage 25 to providehigh level output color signals R, G and B to respective intensitycontrol electrodes of a color image reproducing kinescope 28.

Signals from source 10 are also supplied to a sync separator 33 forderiving the horizontal line synchronizing (sync) component of thetelevision signal. The derived sync component is supplied from an outputof sync separator 33 to sync processing and deflection circuits 38.Circuits 38 provide horizontal and vertical deflection signals forapplication to deflection control circuits of receiver kinescope 28, andvertical and horizontal (flyback) blanking signals.

A composite keying signal generator 35 responds to output signals fromsync separator 33, and to horizontal and vertical retrace blankingsignals from deflection circuits 38. A composite ("sandcastle") keyingsignal output from generator 35 is supplied via a terminal 6 to a signaldecoder 40, which decodes the composite keying signal into separatekeying pulses V_(b), V_(C), V_(K) and V_(H), V_(V) as required by keyedsignal processing circuits within network 11. Decoder 40 is shown indetail in copending U.S. patent application Ser. No. 113,371 of R. L.Shanley, II, et al. noted previously.

Keying pulses V_(B) and V_(C) encompass the burst interval and exhibit amutually antiphase (push-pull) relationship, and are applied to keyinginputs of chroma-burst separator 15. Keying pulse V_(K) is in-phase withand of the same (positive) polarity as pulse V_(B), and is applied to akeying input of comparator 30. Plural keying pulses V_(H), V_(V) occurduring each horizontal and vertical image retrace interval, and areapplied to respective plural keying inputs of output stage 25.

In the arrangement of FIG. 1, the blocks within network 11 are largelycapable of being fabricated as a single integrated circuit. In suchcase, terminals 1-6 correspond to external connecting terminals of theintegrated circuit.

FIG. 2 shows a circuit arrangement of composite keying signal generator35 in FIG. 1. In circuit 35, a base input of a normally nonconductiveswitching transistor 50 receives positive horizontal sync pulses fromthe output of sync separator 33 via an input coupling and timing network55. A resonant circuit comprising a capacitor 57 and an inductor 58 isincluded in the collector output circuit of transistor 50 together witha load resistor 59. As disclosed in U.S. Pat. No. 4,051,518--Sendelweck,the resonant circuit is excited into ringing at its natural frequencywhen transistor 50 is keyed to conduct. The period of the ringing signalis determined by the values of capacitor 57 and inductor 58. A resultingoutput ringing signal in the collector circuit of transistor 50 coactswith the inverse conduction characteristic of transistor 50 to turn offtransistor 50 prior to the completion of one full cycle of ringing, sothat a positive burst gate pulse produced at the junction of capacitor57 and inductor 58 corresponds to the first full half cycle (of positivepolarity) of the ringing signal. The positive output pulse occurs overinterval T_(K) within horizontal retrace interval T_(H), and encompassesthe burst interval.

The output gate pulse provided by transistor 50 is coupled to a signalcombining point A via a diode 62 and a resistor 66 included in theoutput circuit of the gate pulse generator comprising transistor 50.Signals developed at point A are coupled to an output terminal T_(O) ofcircuit 35 via a diode 69.

A network 80 including a horizontal flyback transformer 82 provides ahorizontal timing signal including positive horizontal flyback pulsesduring each horizontal retrace blanking interval T_(H) (encompassinginterval T_(K)). Transformer 82 includes a primary winding and asecondary winding with a grounded center tap. The flyback signal appearsat a terminal T₁ of the secondary winding.

A diode 85 in the flyback signal path is rendered nonconductive duringeach horizontal blanking interval T_(H) in response to the positiveflyback pulse during interval T_(H). Circuit 35 then produces a firstvoltage level at point A. The gate pulse from transistor 50 also occurswithin blanking interval T_(H), during interval T_(K), and combines withthe first voltage level to develop a composite ("sandcastle") keyingsignal at point A. The composite keying signal is coupled via diode 69to an output terminal T_(O) of circuit 35. A first signal translatingvoltage divider comprising resistors 65, 66, 67 and a second signaltranslating voltage divider including resistors 72, 73, 74 are includedto establish appropriate levels of the composite keying signal thatappears at output terminal T_(O).

Thus the composite output keying signal developed by circuit 35 includesfirst and second pulse components. During each horizontal retraceblanking interval T_(H), the first (lower) pulse with a blankingpedestal level of approximately +2.5 volts is produced in response tothe positive flyback pulse that renders diode 85 nonconductive. The gatepulse output of transistor 50 comprises a second (upper) pulse componentof the composite keying signal. The second pulse is superimposed on thefirst pulse component during interval T_(K).

Analogous observations pertain with respect to generating a compositevertical blanking signal during vertical blanking interval T_(V). Duringeach vertical retrace blanking interval T_(V), a positive-going verticalblanking pulse is coupled to a terminal T₂. This pulse is translated byvoltage divider 72, 73, 74 so that a voltage then developed at outputterminal T_(O) corresponds to the desired pedestal level of the lowerpulse component for vertical blanking purposes. The waveforms ofcomposite keying signals developed for horizontal and vertical purposesare shown in detail in aforementioned U.S. patent application Ser. No.113,371 of R. L. Shanley.

The gate pulse generating circuit comprising transistor 50 canundesirably be caused to generate a false output gate pulse in responseto spurious input signals that may appear during picture intervals(T_(I))of the video signal. Such spurious signals can include thermalnoise, and other forms of noise that may be associated with the videosignal and appear at the output of sync separator 33 (FIG. 1).Significant levels of output current can be associated with the falsegate pulse, since in this example the output circuit of transistor 50 iscapable of sourcing peak output currents on the order of tenmilliamperes. Such currents are associated with the output ringingwaveform developed when resonant circuit 57, 58 is excited into ringingby the conduction of transistor 50. False output gate pulses areinhibited in the following manner.

During each horizontal picture interval T_(I), the signal from flybacktransformer 82 exhibits a negative voltage (approximately -7 volts)sufficient to forward bias diode 85 into conduction. When conducting,diode 85 serves to clamp circuit point A (through which output gatepulses from transistor 50 pass) to a voltage of approximately -6.3volts. Therefore, any false gate pulses generated during the pictureintervals are also clamped to this level, which in this example isinsufficient to cause decoder 40 (FIG. 1) to generate improperly timedkeying signals V_(B), V_(C) and V_(K).

Diode 85 is included in a clamping path between point A and ground viaterminal T₁ and the grounded center tap secondary winding of transformer82. Clamp diode 85 represents a switch arranged in series with thesource of flyback switching signals between point A and ground.

The clamping current path exhibits a very low impedance (i.e., a fewohms) relative to the impedance presented by the output circuit of gatepulse generator transistor 50 when conductive during the pictureintervals (approximately 450 ohms). In this regard, it is noted that thecurrent conduction capability of the clamping path between point A andground is greater than the output current conduction capability of thegate pulse generating circuit including transistor 50. This result is afunction of the effective impedance of the clamping path compared to theeffective output impedance of the gate pulse generating circuit, and ofthe amplitude of the flyback switching signal during picture intervalscompared to the amplitude of the gate pulses capable of being generatedby transistor 50 (approximately +8.0 volts in this example).

More specifically, in this example the keyed signal processing circuitsthat respond to keying signals supplied via terminal T_(O) are enabledto operate when the level of the keying pulse generated during keyinginterval T_(K) exceeds an output threshold level of approximately +1.5volts at terminal T_(O) of circuit 35. Therefore in order to preventfalse picture interval keying pulses from being supplied via terminalT_(O), the voltage at point A must be held to a level substantiallyequal to or less than a threshold level of approximately +2.2 volts (the+1.5 volt output threshold level plus the offset voltage of diode 69)during picture intervals. This result is accomplished when the followingrelationship is satisfied:

    V.sub.A =(R.sub.C V.sub.BG -R.sub.BG V.sub.C)/(R.sub.C +R.sub.BG)≦V.sub.T

where

V_(A) is the voltage at point A,

V_(T) is the threshold voltage that must not be exceeded at point A,

V_(BG) is the magnitude of output gate pulses capable of being generatedby the burst gate pulse generator circuit including transistor 50,

V_(C) is the clamping voltage developed at point A by the clamp networkincluding diode 85,

R_(BG) is the effective output impedance of the burst gate pulsegenerator circuit; and

R_(C) is the effective impedance of the clamping circuit including diode85.

Accordingly, the clamping current path is capable of conducting away("sinking") from point A those currents that are expected to beconducted ("sourced") from the output circuit of the gate pulsegenerator when false picture interval gate pulses are generated. Circuitpoint A therefore remains clamped and false gate pulses are preventedfrom passing to output terminal T_(O).

It is also noted that the above result is aided by the manner in whichclamping currents conducted by diode 85 and (false) output gate pulsecurrents conducted by resistor 66 during picture intervals are poled.Specifically, clamping currents flow from point A to ground via diode85. Gate pulse current flows to point A so that this current adds torather than subtracts from the clamping current. Consequently, the gatepulse current does not oppose the clamping current, and desirably servesto assure that the clamping current is maintained above a minimum levelrather than diminished.

What is claimed is:
 1. In a television receiver for processing acomposite television signal containing image information occurringduring periodic horizontal image intervals and horizontal synchronizinginformation occurring during periodic horizontal image blankingintervals; said receiver including means for providing a horizontalreference pulse representative of said horizontal synchronizinginformation; means for providing a horizontal timing signal comprisingimage and blanking interval components subject to synchronization bysaid horizontal synchronizing information; and keyed signal processingcircuits; apparatus for generating an output keying signal during saidblanking intervals, said apparatus comprising:keyed means, subject toswitching between first and second switching states and coupled to saidhorizontal reference pulse providing means, for generating said keyingsignal, said keyed means including an output circuit coupled to acircuit point and exhibiting said second switching state during eachreference pulse appearance; means for coupling keying signals from saidcircuit point to said keyed signal processing circuits; and controlmeans coupled to said circuit point and responsive to said horizontaltiming signal for inhibiting false keying signal outputs from said keyedmeans during said image intervals, said control means exhibiting anonconductive condition during said blanking intervals, and exhibiting aconductive condition during said image intervals; and wherein thecurrent conduction capability of said control means during said imageintervals substantially equals or exceeds the current conductioncapability of said output circuit of said keyed means.
 2. Apparatusaccording to claim 1, wherein:said control means exhibits a lowerimpedance during said image intervals than the impedance presented bysaid output circuit when said keyed means exhibits said second switchingstate.
 3. Apparatus according to claim 1, wherein:said control meanscomprises controllable conduction clamping means included in a clampingcurrent path coupled between said circuit point and a point of referencepotential, said clamping current path exhibiting a lower impedanceduring said image intervals than the impedance presented by said outputcircuit when said keyed means exhibits said second switching state. 4.Apparatus according to claim 3, wherein:said clamping means and saidmeans for providing said horizontal timing signals are arranged inseries between said circuit point and a point of reference potential. 5.Apparatus according to claim 3 or 4, wherein:said keyed means and saidclamping means are arranged so that currents conducted by said outputcircuit of said keyed means in response to false keying signals, whenpresent during said image intervals, are poled so as to reinforcecurrents conducted by said clamping means during said image intervals.6. In a television receiver for processing a composite television signalcontaining image information occurring during periodic horizontal imageintervals and horizontal synchronizing information occurring duringperiodic horizontal image blanking intervals, said receiver includingmeans for providing a horizontal reference pulse representative of saidhorizontal synchronizing information; means for providing a horizontaltiming signal comprising image and blanking interval components subjectto synchronization by said horizontal synchronizing information; andkeyed signal processing circuits; apparatus for generating a keyingsignal during said blanking intervals; said apparatus comprising:keyedmeans subject to switching between first and second switching states andcoupled to said horizontal reference pulse providing means, forgenerating said keying signal, said keyed means including an outputcircuit coupled to a circuit point and exhibiting said second switchingstate during each reference pulse appearance; means for coupling keyingsignals from said circuit point to said keyed signal processingcircuits; and clamping means responsive to said horizontal timing signaland included in a clamping conduction path between said circuit pointand a point of reference potential for inhibiting false keying signaloutputs from said keyed means during said image intervals, said clampingmeans exhibiting a nonconductive condition during said blankingintervals, and exhibiting a conductive condition during said imageintervals; and wherein said clamping means and said output circuit ofsaid keyed means are coupled to said circuit point so that currentsconducted by said output circuit of said keyed means in response tofalse keying signals, when present during said image intervals, arepoled so as to reinforce currents conducted by said clamping meansduring said image intervals.
 7. In a color television receiver forprocessing a composite color television signal containing imageinformation occurring during periodic horizontal image intervals andsynchronizing information occurring during periodic image blankingintervals, said synchronizing information including: a horizontalsynchronizing component occurring during horizontal blanking intervals,and a color burst component occurring during a burst interval withinhorizontal blanking intervals; said receiver including means forproviding a horizontal reference pulse representative of said horizontalsynchronizing component; means for providing a horizontal timing signalcomprising image and blanking interval components subject tosynchronization by said horizontal synchronizing component; and keyedsignal processing circuits; apparatus for generating an output compositekeying signal comprising a first pulse substantially coincident withsaid horizontal blanking intervals and a second pulse superimposed onsaid first pulse and encompassing said burst interval, said apparatuscomprising:means responsive to said horizontal timing signal forgenerating said first pulse during said horizontal blanking intervals;keyed means, subject to switching between first and second switchingstates and coupled to said horizontal reference pulse providing meansfor providing, via an output circuit, a pulse encompassing said burstinterval and corresponding to said second pulse, said keyed meansexhibiting said second switching state during each reference pulseappearance; means for combining said first and second pulses to producesaid composite keying signal at a circuit point; means for coupling saidcomposite keying signal from said circuit point to said keyed signalprocessing circuits; and control means coupled to said circuit point andresponsive to said horizontal timing signal for inhibiting false keyingsignal outputs from said keyed means during said image intervals, saidcontrol means exhibiting a nonconductive state during said blankingintervals, and exhibiting a conductive state during image intervals; andwherein the currrent conduction capability of said control means duringsaid image intervals substantially equals or exceeds the currentconduction capability of said output circuit of said keyed means. 8.Apparatus according to claim 7, wherein:said control means exhibits alower impedance during said image intervals than the impedance presentedby said output circuit of said keyed means when said keyed meansexhibits said second switching state.
 9. Apparatus according to claim 7,wherein:said control means comprises controllable conduction clampingmeans included in a clamping current path coupled between said circuitpoint and a point of reference potential, said clamping current pathexhibiting a lower impedance during said image intervals than theimpedance presented by said output circuit of said keyed means when saidkeyed means exhibits said second switching state.
 10. Apparatusaccording to claim 9, wherein:a low impedance path is provided betweensaid circuit point and a point of reference potential during said imageintervals by the series combination of said clamping means and saidmeans for providing said timing signal.
 11. Apparatus according to claim9 or 10, wherein:said clamping means and said output circuit of saidkeyed means are coupled to said circuit point so that currents conductedby said output circuit of said keyed means in response to false keyingsignals, when present during said image intervals, are poled so as toreinforce currents conducted by said clamping means during said imageintervals.
 12. In a color television receiver for processing a compositecolor television signal containing image information occurring duringperiodic horizontal image intervals and synchronizing informationoccurring during periodic image blanking intervals, said synchronizinginformation including: a horizontal synchronizing component occurringduring horizontal blanking intervals, and a color burst componentoccurring during a burst interval within horizontal blanking intervals;said receiver including means for providing a horizontal reference pulserepresentative of said horizontal synchronizing component; means forproviding a horizontal timing signal comprising image and blankinginterval components subject to synchronization by said horizontalsynchronizing component; and keyed signal processing circuits; apparatusfor generating an output composite keying signal comprising a firstpulse substantially coincident with said horizontal blanking intervalsand a second pulse superimposed on said first pulse and encompassingsaid burst interval, said apparatus comprising:means responsive to saidhorizontal timing signal for generating said first pulse during saidhorizontal blanking intervals; keyed means subject to switching betweenfirst and second switching states and coupled to said horizontalreference pulse providing means for providing, via an output circuit, apulse encompassing said burst interval and corresponding to said secondpulse, said keyed means exhibiting said second switching state duringeach reference pulse appearance; means for combining said first andsecond pulses to produce said composite keying signal at a circuitpoint; means for coupling said composite keying signal from said circuitpoint to said keyed signal processing circuits; and clamping meansresponsive to said horizontal timing signal and included in a clampingcurrent conduction path between said circuit point and a point ofreference potential for inhibiting false keying signal outputs from saidkeyed means during said image intervals, said clamping means exhibitinga nonconductive condition during said blanking intervals, and aconductive condition during said image intervals; and wherein saidclamping means and said output circuit of said keyed means are coupledto said circuit point so that currents conducted by said output circuitin response to false keying signals, when present during said imageintervals, are poled so as to reinforce currents conducted by saidclamping means during said image intervals.
 13. In a television receiverfor processing a composite television signal containing imageinformation occurring during periodic image intervals and horizontalsynchronizing information occurring during periodic horizontal imageblanking intervals, said receiver including means for providing ahorizontal reference pulse representative of said horizontalsynchronizing information; and signal processing circuits responsive tokeying signals during said blanking intervals; apparatus for generatingsaid keying signals, comprising:a switching device operable betweenfirst and second switching states and coupled to said source ofhorizontal reference pulses for generating said keying signals, saidswitching device including an output circuit coupled to a circuit pointvia a keying signal conduction path and exhibiting said second switchingstate during each reference pulse appearance; a horizontal timingnetwork including a horizontal flyback transformer having a primarywinding, and an output secondary winding for providing a horizontalflyback signal with image and blanking interval components and subjectto synchronization by said horizontal synchronizing information; and aclamping network for inhibiting false keying signal outputs from saidswitching device during said image intervals, said clamping networkcomprising a unilateral current conducting clamping device included in aclamping conduction path comprising said secondary winding of saidflyback transformer between said circuit point and a point of referencepotential, said clamping device being rendered nonconductive in responseto said blanking interval component of said flyback signal and beingrendered conductive in response to said image interval component of saidflyback signal; and wherein said clamping path conducts clamping currentbetween said circuit point and said point of reference potential, andsaid keying signal path conducts current from said output circuit tosaid circuit point so that false keying signal currents conducted inresponse to false keying signals, when present during said imageintervals, reinforce clamping currents conducted by said clamping pathduring said image intervals.
 14. Apparatus according to claim 13,wherein:said switching device comprises a transistor with a base inputcoupled to said source of horizontal reference pulses, and acollector-emitter path coupled to said output circuit; and saidunilateral current conducting clamping device comprises a diode poledfor forward current conduction from said circuit point to said point ofreference potential via said transformer secondary winding.